1. Field of Invention
The present invention relates to an active device array substrate and a manufacturing method thereof, and particularly to a thin film transistor array substrate and a manufacturing method thereof.
2. Description of the Related Art
Display is a communication interface between human and information. Nowadays, the flat display has become the trend of development in the display field. The flat panel display primarily includes: organic electroluminescence display (OLED), plasma display panel (PDP), and thin film transistor liquid crystal display (TFT-LCD). Wherein, the thin film transistor liquid crystal display is applied most generally.
The thin film transistor liquid crystal display mainly comprises a thin film transistor array substrate, a color filter, and a liquid crystal layer. The thin film transistor array substrate comprises a plurality of pixel units arranged in an array, wherein every pixel unit is composed of thin film transistor and a data line, a scan line, and a pixel electrode electrically connected thereto. The foregoing thin film transistor comprises a gate, a channel layer, a source and a drain, and is used as a switch for the pixel unit.
FIG. 1A is a top view of a conventional thin film transistor array substrate. FIG. 1B is a cross-sectional diagram along the line A-A′ in FIG. 1A. As shown in FIG. 1A and FIG. 1B, a first metal layer 110 is disposed on a substrate 102, wherein the first metal layer 110 comprises scan lines 112, gates 114, and common lines 116. Besides, a gate isolating layer 120 covers the first metal layer 110, wherein the material of the gate isolating layer 120 may be silicon nitride. Moreover, channel layers 132 are disposed on the gate isolating layer 120 and corresponding to the gates 114. A second metal layer 140 is disposed on the substrate 102, wherein the second metal layer 140 comprises data lines 142, sources 144a, and drains 144b. 
Referring to FIG. 1A and FIG. 1B, the source 144a and drain 144b are disposed on both sides of the channel layer 132 above the gate 114. The gate 114, the channel layer 132, the source 144a, and the drain 144b form a thin film transistor 146. In addition, a passivation layer (not shown) is disposed on the first metal layer 110, the gate insulating layer 120, and the second metal layer 140, wherein the passivation layer (not shown) comprises an opening 152 in which the drain 144b exposes. Besides, a pixel electrode 162 is disposed on the passivation layer and electrically connected with the drain 144b through the opening 152. Moreover, conventionally, for reducing the probability of producing current leakage due to incomplete back channel etching during patterning second metal layer 140, a semiconductor layer 134 is reserved under the data line 142 when making channel layer 132.
According to the above description, the conventional manufacture or use of the thin film transistor array substrate generally has defects such as:
1. During the manufacturing process of the thin film transistor array substrate, a plasma bombard is employed to produce charges of gas molecules in the step of dry etching, and thus the charges may accumulate easily. After a period of time, the accumulated charges may punch through the formed metal layer, so as to form a short circuit between the first metal layer and the second metal layer.
2. The excess semiconductor material under the pixel electrode may lead to defects or brightness dots during display.
3. The data line is disposed on the semiconductor layer. However, the data line is formed of material such as chromium (Cr), molybdenum (Mo), or wolfram (W), which has low adhesion with amorphous silicon. Therefore, the data lines may be easily broken in the manufacturing process.